P-MOS tutorial on ON-OFF ratio

on-off ratio of MOS transistor analysis

MOS Transistor Definitions

• n-type MOS: Majority carriers are electrons.
• p-type MOS: Majority carriers are holes.

• Positive/negative voltage applied to the gate (with respect to substrate) enhances the number of electrons/holes in the channel and increases conductivity between source and drain.

• V _t defines the voltage at which a MOS transistor begins to conduct. For voltages less than V _t (threshold voltage), the channel is cut off.

MOS Transistor Definitions

• In normal operation, a positive voltage applied between source and drain (V _ds ).
• No current flows between source and drain (I _ds = 0) with V _gs = 0 because of back to back pn junctions.

• For n-MOS, with V _gs > V _tn , electric field attracts electrons creating channel.
• Channel is p-type silicon which is inverted to n-type by the electrons attracted by the electric field.

n-MOS Enhancement Transistor Physics

• Three modes based on the magnitude of V _gs : accumulation, depletion and inversion.

n-MOS Enhancement Transistor Physics

n-MOS Enhancement Transistor

• With V _ds non-zero, the channel becomes smaller closer to the drain.

• When V _ds <= V _gs - V _t (e.g. V _ds = 3V, V _gs = 5V and V _t = 1V), the channel reaches the drain (since V _gd > V _t ).

• This is termed linear , resistive or nonsaturated region. I _ds is a function of both V _gs and V _ds .

n-MOS Enhancement Transistor

• When V _ds > V _gs - V _t (e.g. V _ds = 5V, V _gs = 5V and V _t = 1V), the channel is pinched off close to the drain (since V _gd <> _t ).

• This is termed saturated region. I _ds is a function of V _gs , almost independent of V _ds .

MOS Enhancement Transistor

• MOS transistors can be modeled as a voltage controlled switch. I _ds is an important parameter that determines the behavior, e.g., the speed of the switch.

• What are the parameters that effect the magnitude of I _ds ? (Assume V _gs and V _ds are fixed, e.g. 5V).
• The distance between source and drain (channel length).
• The channel width.
• The threshold voltage.
• The thickness of the gate oxide layer.
• The dielectric constant of the gate insulator.
• The carrier (electron or hole) mobility.

• Summary of normal conduction characteristics:
• Cut-off : accumulation, I _ds is essentially zero.
• Nonsaturated : weak inversion, I _ds dependent on both V _gs and V _ds .
• Saturated : strong inversion, I _ds is ideally independent of V _ds .

Threshold Voltage

• V _t is also an important parameter. What effects its value?

• Most are related to the material properties. In other words, V _t is largely determined at the time of fabrication, rather than by circuit conditions, like I _ds .

• For example, material parameters that effect V _t include:
• The gate conductor material (poly vs. metal).
• The gate insulation material (SiO ₂ ).
• The thickness of the gate material.
• The channel doping concentration.

• However, V _t is also dependent on
• V _sb (the voltage between source and substrate), which is normally 0 in digital devices.
• Temperature: changes by -2mV/degree C for low substrate doping levels.

Threshold Voltage

• The expression for threshold voltage is given as:

Threshold Voltage

• Threshold voltage (cont.):

• Typical values of V _t for n and p-channel transistors are +/- 700mV.

Threshold Voltage

• From equations, threshold voltage may be varied by changing:
• The doping concentration (N _A ).
• The oxide capacitance (C _ox ).
• Surface state charge (Q _fc ).

• As you can see, it is often necessary to adjust V _t .
• Two methods are common:
• Change Q _fc by introducing a small doped region at the oxide/substrate interface via ion implantation.

• Change C _ox by using a different insulating material for the gate.
• A layer of Si ₃ N ₄ (silicon nitride) with a relative permittivity of 7.5 is combined with a layer of silicon dioxide (relative permittivity of 3.9).
• This results in a relative permittivity of about 6.

• For the same thickness dielectric layer, C _ox is larger using the combined material, which lowers V _t .

Body Effect

• In digital circuits, the substrate is usually held at zero.
• The sources of n-channel devices, for example, are also held at zero, except in cases of series connections, e.g.,

• The source-to-substrate (V _sb ) may increase at this connections, e.g. V _sbN1 = 0 but V _sbN2 /= 0.
• V _sb adds to the channel-substrate potential:

Basic DC Equations

• Ideal first order equation for cut-off region:

• Ideal first order equation for linear region:

• Ideal first order equation for saturation region:

• with the following definitions:

Basic DC Equations

• Process dependent factors: .

• Geometry dependent factors: W and L.

• Voltage-current characteristics of the n- and p-transistors.

Beta calculation

• Transistor beta calculation example:
• Typical values for an n-transistor in 1 micron technology:

• Compute beta:

• How does this beta compare with p-devices:

• n-transistor gains are approximately 2.8 times larger than p-transistors.

Inverter voltage transistor characteristics

• Inverter DC characteristics

Beta Ratios

• Region C is the most important region. A small change in the input voltage, V _in , results in a LARGE change in the output voltage, V _out .

• This behavior describes an amplifier, the input is amplified at the output. The amplification is termed transistor gain, which is given by beta.

• Both the n and p-channel transistors have a beta. Varying their ratio will change the characteristics of the output curve.

Beta Ratios

• Therefore, the

• does NOT affect switching performance.

• What factor would argue for a ratio of 1 for ?

• Load capacitance !

• The time required to charge or discharge a capacitive load is equal when .

• Since beta is dependent W and L, we can adjust the ratio by changing the sizes of the transistor channel widths, by making p-channel transistors wider than n-channel transistors.

Noise Margins

• A parameter that determines the maximum noise voltage on the input of a gate that allows the output to remain stable.

• Two parameters, Low noise margin (NM _L ) and High noise margin (NM _H ).

• NM _L = difference in magnitude between the max LOW output voltage of the driving gate and max LOW input voltage recognized by the driven gate.

Noise Margins

• Ideal characteristic: V _IH = V _IL = (V _OH +V _OL )/2.

• This implies that the transfer characteristic should switch abruptly (high gain in the transition region).

• V _IL found by determining unity gain point from V _OH .

Pseudo-nMOS Inverter

• Therefore, the shape of the transfer characteristic and the V _OL of the inverter is affected by the ratio .

• In general, the low noise margin is considerably worse than the high noise margin for Pseudo-nMOS.

• Pseudo-nMOS was popular for high-speed circuits, static ROMs and PLAs.

Pseudo-nMOS

• Example: Calculation of noise margins:

• The transfer curve for the pseudo-nMOS inverter can be used to calculate the noise margins of identical pseudo-nMOS inverters.